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semiconductor technical data 1 rev 2 ? motorola, inc. 1995 10/95
highperformance silicongate cmos the mc54/74hct161a and hct163a are identical in pinout to the ls161a and ls163a. these devices may be used as level converters for interfacing ttl or nmos outputs to high speed cmos inputs. the hct161a and hct163a are programmable 4bit binary counters with asynchronous and synchronous reset, respectively. ? output drive capability: 10 lsttl loads ? ttl, nmos compatible input levels ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 4.5 to 5.5 v ? low input current: 1 m a ? high noise immunity characteristic of cmos devices ? in compliance with the requirements defined by jedec standard no. 7a ? chip complexity: 200 fets or 50 equivalent gates logic diagram reset preset data inputs pin 16 = vcc pin 8 = gnd 1 p 3 6 p 2 5 p 1 4 p 0 3 clock 2 q 3 11 q 2 12 q 1 13 q 0 14 reset 1 load 9 enable p 7 enable t 10 bcd or binary outputs count enables ripple carry out 15 function table inputs output q clock reset* load enable p enable t output q l h h h h x l h h h x x h l x x x h x l reset load preset data count no count no count h = high level; l = low level; x = don't care * = hct163a only. hct161a is an aasynchronousreseto device.

device count mode reset mode hct161a hct163a binary binary asynchronous synchronous d suffix soic package case 751b05 n suffix plastic package case 64808 ordering information mc54hcxxxaj mc74hcxxxan mc74hcxxxad ceramic plastic soic 1 16 1 16 j suffix ceramic package case 62010 1 16 pinout: 16lead package (top view) 15 16 14 13 12 11 10 2 1 3 4 5 6 7 v cc 9 8 rco* q 0 q 1 q 2 q 3 enable t load reset clock p 0 p 1 p 2 p 3 enable p gnd * rco = ripple carry out
mc54/74hct161a mc54/74hct163a motorola highspeed cmos logic data dl129 e rev 6 2 ??????????????????????? ??????????????????????? ??????????????????????? ??????????????????????? maximum ratings* ??? ??? ??? ??? symbol ?????????????? ?????????????? ?????????????? ?????????????? parameter ?????? ?????? ?????? ?????? value ??? ??? ??? ??? unit ??? ??? ??? ??? v cc ?????????????? ?????????????? ?????????????? ?????????????? positive dc supply voltage (referenced to gnd) ?????? ?????? ?????? ?????? 0.5 to + 7.0 ??? ??? ??? ??? v ??? ??? ??? ??? v in ?????????????? ?????????????? ?????????????? ?????????????? dc input voltage (referenced to gnd) ?????? ?????? ?????? ?????? 1.5 to v cc + 1.5 ??? ??? ??? ??? v ??? ??? ??? ??? v out ?????????????? ?????????????? ?????????????? ?????????????? dc output voltage (referenced to gnd) ?????? ?????? ?????? ?????? 0.5 to v cc + 0.5 ??? ??? ??? ??? v ??? ??? ??? ??? i in ?????????????? ?????????????? ?????????????? ?????????????? dc input current, per pin ?????? ?????? ?????? ?????? 20 ??? ??? ??? ??? ma ??? ??? ??? ??? i out ?????????????? ?????????????? ?????????????? ?????????????? dc output current, per pin ?????? ?????? ?????? ?????? 25 ??? ??? ??? ??? ma ??? ??? ??? ??? i cc ?????????????? ?????????????? ?????????????? ?????????????? dc supply current, v cc and gnd pins ?????? ?????? ?????? ?????? 50 ??? ??? ??? ??? ma ??? ??? ??? ??? ??? p d ?????????????? ?????????????? ?????????????? ?????????????? ?????????????? power dissipation in still air, plastic or ceramic dip2 soic package2 ?????? ?????? ?????? ?????? ?????? 750 500 ??? ??? ??? ??? ??? mw ??? ??? ??? ??? t stg ?????????????? ?????????????? ?????????????? ?????????????? storage temperature range ?????? ?????? ?????? ?????? 65 to + 150 ??? ??? ??? ??? c ??? ??? ??? ??? ??? t l ?????????????? ?????????????? ?????????????? ?????????????? ?????????????? lead t emperature, 1 mm from case for 10 seconds plastic dip or soic package ceramic dip ?????? ?????? ?????? ?????? ?????? 260 300 ??? ??? ??? ??? ??? c * maximum ratings are those values beyond which damage to the device may occur . functional operation should be restricted to the recommended operating conditions. 2derating e plastic dip: 10 mw/ c from 65 to 125 c ceramic dip: 10 mw/ c from 100 to 125 c soic package: 7 mw/ c from 65 to 125 c for high frequency or heavy load considerations, see chapter 2 of the motorola highspeed cmos data book (dl129/d). recommended operating conditions ???? ???? ???? ???? symbol ?????????????? ?????????????? ?????????????? ?????????????? parameter ??? ??? ??? ??? min ??? ??? ??? ??? max ??? ??? ??? ??? unit ???? ???? ???? ???? v cc ?????????????? ?????????????? ?????????????? ?????????????? dc supply voltage (referenced to gnd) ??? ??? ??? ??? 4.5 ??? ??? ??? ??? 5.5 ??? ??? ??? ??? v ???? ???? ???? ???? v in , v out ?????????????? ?????????????? ?????????????? ?????????????? dc input voltage, output voltage (referenced to gnd) ??? ??? ??? ??? 0 ??? ??? ??? ??? v cc ??? ??? ??? ??? v ???? ???? ???? ???? t a ?????????????? ?????????????? ?????????????? ?????????????? operating temperature, all package types ??? ??? ??? ??? 55 ??? ??? ??? ??? + 125 ??? ??? ??? ??? c ???? ???? ???? ???? t r , t f ?????????????? ?????????????? ?????????????? ?????????????? input rise and fall time (figure 1) ??? ??? ??? ??? 0 ??? ??? ??? ??? 500 ??? ??? ??? ??? ns dc electrical characteristics (voltages referenced to gnd) v cc guaranteed limit symbol parameter test conditions v 55 to 25 c 85 c 125 c unit v ih minimum highlevel input voltage v out = 0.1 v or v cc = 1.0v |i out | 20 m a 4.5 5.5 2.0 2.0 2.0 2.0 2.0 2.0 v v il maximum lowlevel input voltage v out = 0.1 v |i out | 20 m a 4.5 5.5 0.80 0.80 0.80 0.80 0.80 0.80 v v oh minimum highlevel output voltage v in = v ih or v il |i out | 20 m a 4.5 5.5 4.4 5.4 4.4 5.4 4.4 5.4 v v in = v ih or v il |i out | 4.0 ma 4.5 3.98 3.84 3.70 v v ol maximum lowlevel output voltage v in = v ih or v il |i out | 20 m a 4.5 5.5 0.10 0.10 0.10 0.10 0.10 0.10 v v in = v ih or v il |i out | 4.0 ma 4.5 0.26 0.33 0.40 v i in maximum input leakage current v in = v cc or gnd 5.5 0.10 1.00 1.00 m a i cc maximum quiescent supply current (per package) v in = v cc or gnd i out 0 m a 5.5 4 40 160 m a i cc additional quiescent supply current v in = 2.4v, any one input 55 c 25 to +125 c ma i cc additional quiescent supply current any one input v in = v cc or gnd other inputs i out 0 m a 5.5 2.9 2.4 ma note: information on typical parametric values can be found in chapter 2 of the motorola highspeed cmos data book (dl129/d). this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however , precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance cir - cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
mc54/74hct161a mc54/74hct163a highspeed cmos logic data dl129 e rev 6 3 motorola ac electrical characteristics (v cc = 5.0 v 10%: c l = 50 pf, input t r = t f = 6.0 ns) guaranteed limit symbol parameter fig 55 to 25 c 85 c 125 c unit f max maximum clock frequency (50% duty cycle)* 1,7 30 24 20 mhz t plh maximum propagation delay clock to q 1,7 20 23 28 ns t phl 1,7 25 30 32 ns t phl maximum propagation delay reset to q (hct161a only) 2,7 25 29 33 ns t plh maximum propagation delay enable t to ripple carry out 3,7 16 18 20 ns t phl 3,7 21 24 28 ns t plh maximum propagation delay clock to ripple carry out 1,7 22 25 28 ns t phl 1,7 28 33 35 ns t phl maximum propagation delay reset to ripple carry out (hct161a only) 2,7 24 28 32 ns t tlh, t thl maximum output transition time, any output 2,7 15 19 22 ns c in maximum input capacitance 1,7 10 10 10 pf * applies to noncascaded/nonsynchronous clocked configurations only . with synchronously cascaded counters, (1) clock to ripple carry out propagation delays, (2) enable t or enable p to clock setup times, and (3) clock to enable t or enable p hold times determine f max . however, if ripple carry out of each stage is tied to the clock of the next stage (nonsynchronously clocked), the f max in the table above is applicable. see applications information in this data sheet. note: for propagation delays with loads other than 50 pf, and information on typical parametric values, see chapte r 2 o f the motorola high speed cmos data book (dl129/d). c pd power dissipation capacitance (per gate)* typical @ 25 c, v cc = 5.0 v pf c pd power dissipation capacitance (per gate)* 60 pf * used to determine the noload dynamic power consumption: p d = c pd v cc 2 f + i cc v cc . for load considerations, see chapter 2 of the motorola highspeed cmos data book (dl129/d). timing requirements (v cc = 5.0 v 10%: c l = 50 pf, input t r = t f = 6.0 ns) symbol parameter fig. guaranteed limit unit symbol parameter fig. 55 to 25 c 85 c 125 c unit t su minimum setup time, preset data inputs to clock 5 12 18 20 ns minimum setup time, load to clock 5 12 18 20 ns minimum setup time, reset to clock (hct163a only) 4 12 18 20 ns minimum setup t ime, enable t or enable p to clock 6 12 18 20 ns t h minimum hold time, clock to preset data inputs 5 3 3 3 ns minimum hold time, clock to load 5 3 3 3 ns minimum hold time, clock to reset (hct163a only) 4 3 3 3 ns minimum hold time, clock to en t or en p 6 3 3 3 ns t rec minimum recovery time, reset inactive to clock (hct161a only) 2 12 17 23 ns minimum recovery time, load inactive to clock 2 12 17 23 ns t w minimum pulse width, clock 1 12 15 18 ns minimum pulse width, reset (hct161a only) 1 12 15 18 ns t r, t f maximum input rise and fall times 500 500 500 ns
mc54/74hct161a mc54/74hct163a motorola highspeed cmos logic data dl129 e rev 6 4 function description the hct161a/163a are programmable 4bit synchronous counters that feature parallel load, synchronous or asynchro - nous reset, a carry output for cascading and countenable controls. the hct161a and hct163a are binary counters with asynchronous reset and synchronous reset, respectively. inputs clock (pin 2) the internal flipflops toggle and the output count ad - vances with the rising edge of the clock input. in addition, con - trol functions, such as resetting and loading occur with the rising edge of the clock input. in addition, control functions, such as resetting (hct163a) and loading occur with the rising edge of the clock input. preset data inputs p0, p1, p2, p3 (pins 3, 4, 5, 6) these are the data inputs for programmable counting. data on these pins may be synchronously loaded into the internal flipflops and appear at the counter outputs. p0 (pin 3) is the leastsignificant bit and p3 (pin 6) is the mostsignificant bit. outputs q0, q1, q2, q3 (pins 14, 13, 12, 11) these are the counter outputs. q0 (pin 14) is the leastsig - nificant bit and q3 (pin 11) is the mostsignificant bit. ripple carry out (pin 15) when the counter is in its maximum state 1 11 1, this output goes high, providing an external lookahead carry pulse that may be used to enable successive cascaded counters. ripple carry out remains high only during the maximum count state. the logic equation for this output is: ripple carry out = enable t ? q0 ? q1 ? q2 ? q3 control functions resetting a low level on the reset pin (pin 1) resets the internal flip flops and sets the outputs (q0 through q3) to a low level. the hct161a resets asynchronously , and the hct163a resets with the rising edge of the clock input (synchronous reset). loading with the rising edge of the clock, a low level on load (pin 9) loads the data from the preset data input pins (p0, p1, p2, p3) into the internal flipflops and onto the output pins, q0 through q3. the count function is disabled as long as load is low. count enable/disable these devices have two countenable control pins: enable p (pin 7) and enable t (pin 10). the devices count when these two pins and the load pin are high. the logic equation is: count enable = enable p ? enable t ? load the count is either enabled or disabled by the control inputs according to t able 1. in general, enable p is a countenable control: enable t is both a countenable and a ripplecarry output control. table 1. count enable/disable control inputs result at outputs load enable p enable t q0q3 ripple carry out h h h count high when q0q3 l h h no count are maximum* x l h no count high when q0q3 are maximum* x x l no count l q0 through q3 are maximum when q3 q2 q1 q0 = 1111. output state diagram binary counters 0 15 14 13 12 1 2 3 4 5 6 7 8 11 10 9
mc54/74hct161a mc54/74hct163a highspeed cmos logic data dl129 e rev 6 5 motorola switching waveforms t r figure 1. clock any output 3.0v gnd 90% 1.3v 10% t f t w 90% 1.3v 10% t phl 1/f max t plh t tlh t thl reset 3.0v gnd t w any output 3.0v gnd clock figure 2. t phl t rec 1.3v 1.3v 1.3v figure 3. t r enable t 3.0v gnd 90% 1.3v 10% t f ripple carry out 90% 1.3v 10% t thl t tlh t phl t plh figure 4. hct163a only reset 3.0v gnd t h 3.0v gnd clock t su 1.3v 1.3v load 3.0v gnd 3.0v gnd clock t su 1.3v 1.3v figure 5. inputs p 0 , p 1 , p 2 , p 3 3.0v gnd 1.3v t su t h t h t rec 3.0v gnd 1.3v enable t or enable p 3.0v gnd 1.3v t h t su valid clock figure 6. figure 7. test circuit c l * *includes all probe and jig capacitance test point device under test output
mc54/74hct161a mc54/74hct163a motorola highspeed cmos logic data dl129 e rev 6 6 14 q 0 3 p 0 t0 r c c load load p0 q0 q0 13 q 1 t1 r c c load load p1 q1 q1 12 q 2 t2 r c c load load p2 q2 q2 4 p 1 5 p 2 11 q 3 t3 r c c load load p3 q3 6 p 3 15 ripple carry out 7 enable p 10 enable t 1 reset 9 load 2 clock r load load c c the flipflops shown in the circuit diagrams are toggle enable flipflops. a t oggleenable flipflop is a combina - tion of a d flipflop and a t flipflop. when loading data from preset inputs p 0 , p 1 , p 2 and p 3 , the load signal is used to disable the t oggle input (t n ) of the flipflop. the logic level at the p n input is then clocked to the q output of the flipflop on the next rising edge of the clock. a logic zero on the reset device input forces the internal clock (c) high and resets the q output of the flipflop low. figure 8. 4bit binary counter with asynchronous reset (mc54/74hct161a)
mc54/74hct161a mc54/74hct163a highspeed cmos logic data dl129 e rev 6 7 motorola figure 9. timing diagram reset (hct161a) reset (hct163a) load p0 p1 p2 p3 clock (hct161a) clock (hct163a) enable p enable t q0 q1 q2 q3 ripple carry out count inhibit reset load 12 13 14 15 0 1 2 (asynchronous) (synchronous) preset data inputs outputs count enables
mc54/74hct161a mc54/74hct163a motorola highspeed cmos logic data dl129 e rev 6 8 14 q 0 3 p 0 t0 r c c load load p0 q0 q0 13 q 1 t1 r c c load load p1 q1 q1 12 q 2 t2 r c c load load p2 q2 q2 4 p 1 5 p 2 11 q 3 t3 r c c load load p3 q3 6 p 3 15 ripple carry out 7 enable p 10 enable t 1 reset 9 load 2 clock r load load c c the flipflops shown in the circuit diagrams are toggle enable flipflops. a t oggleenable flipflop is a combina - tion of a d flipflop and a t flipflop. when loading data from preset inputs p 0 , p 1 , p 2 and p 3 , the load signal is used to disable the t oggle input (t n ) of the flipflop. the logic level at the p n input is then clocked to the q output of the flipflop on the next rising edge of the clock. a logic zero on the reset device input forces the internal clock (c) high and resets the q output of the flipflop low. figure 10. 4bit binary counter with synchronous reset (mc54/74hct163a)
mc54/74hct161a mc54/74hct163a highspeed cmos logic data dl129 e rev 6 9 motorola typical applications cascading figure 11. nbit synchronous counters enable p enable t clock reset q 0 q 1 q 2 q 3 load q 0 q 1 q 2 q 3 ripple carry out inputs outputs enable p enable t clock reset q 0 q 1 q 2 q 3 load q 0 q 1 q 2 q 3 ripple carry out inputs outputs enable p enable t clock reset q 0 q 1 q 2 q 3 load q 0 q 1 q 2 q 3 ripple carry out inputs outputs to more significant stages load h=count l=disable h=count l=disable reset clock note: when used in these cascaded configurations the clock f max guaranteed limits may not apply . actual performance will depend on number of stages. this limitation is due to setup times between enable (port) and clock. figure 12. nibble ripple counter enable p enable t clock reset q 0 q 1 q 2 q 3 load q 0 q 1 q 2 q 3 ripple carry out inputs outputs enable p enable t clock reset q 0 q 1 q 2 q 3 load q 0 q 1 q 2 q 3 ripple carry out inputs outputs enable p enable t clock reset q 0 q 1 q 2 q 3 load q 0 q 1 q 2 q 3 ripple carry out inputs outputs to more significant stages enable p reset clock enable t load
mc54/74hct161a mc54/74hct163a motorola highspeed cmos logic data dl129 e rev 6 10 typical applications varying the modulus figure 13. modulo5 counter figure 14. modulo11 counter other inputs q0 q1 q2 q3 reset output hct163a optional buffer for noise rejection other inputs q0 q1 q2 q3 reset output hct163a optional buffer for noise rejection the hct163a facilitates designing counters of any modulus with minimal external logic. the output is glitch free due to the synchronous reset.
mc54/74hct161a mc54/74hct163a highspeed cmos logic data dl129 e rev 6 11 motorola outline dimensions j suffix ceramic package case 62010 issue v n suffix plastic package case 64808 issue r 19.05 6.10 e 0.39 1.40 0.21 3.18 19.93 7.49 5.08 0.50 1.65 0.38 4.31 0 0.51 15 1.01 1.27 bsc 2.54 bsc 7.62 bsc min min max max inches millimeters dim 0.750 0.240 e 0.015 0.055 0.008 0.125 0.785 0.295 0.200 0.020 0.065 0.015 0.170 0.050 bsc 0.100 bsc 0.300 bsc a b c d e f g j k l m n 0 0.020 15 0.040 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dim f may narrow to 0.76 (0.030) where the lead enters the ceramic body. 1 8 9 16 a b c k n g e f d 16 pl t seating plane m l j 16 pl 0.25 (0.010) t a m s 0.25 (0.010) t b m s min min max max inches millimeters dim a b c d f g h j k l m s 18.80 6.35 3.69 0.39 1.02 0.21 2.80 7.50 0 0.51 19.55 6.85 4.44 0.53 1.77 0.38 3.30 7.74 10 1.01 0.740 0.250 0.145 0.015 0.040 0.008 0.110 0.295 0 0.020 0.770 0.270 0.175 0.021 0.070 0.015 0.130 0.305 10 0.040 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. 2.54 bsc 1.27 bsc 0.100 bsc 0.050 bsc a b 1 8 9 16 f h g d 16 pl s c t seating plane k j m l t a 0.25 (0.010) m m 0.25 (0.010) t b a m s s min min max max millimeters inches dim a b c d f g j k m p r 9.80 3.80 1.35 0.35 0.40 0.19 0.10 0 5.80 0.25 10.00 4.00 1.75 0.49 1.25 0.25 0.25 7 6.20 0.50 0.386 0.150 0.054 0.014 0.016 0.008 0.004 0 0.229 0.010 0.393 0.157 0.068 0.019 0.049 0.009 0.009 7 0.244 0.019 1.27 bsc 0.050 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 1 8 9 16 a b d 16 pl k c g t seating plane r x 45 m j f p 8 pl 0.25 (0.010) b m m d suffix plastic soic package case 751b05 issue j
mc54/74hct161a mc54/74hct163a motorola highspeed cmos logic data dl129 e rev 6 12 how to reach us: usa/europe : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, toshikatsu otsuki, p.o. box 20912; phoenix, arizona 85036. 18004412447 6f seibubutsuryucenter, 3142 tatsumi kotoku, tokyo 135, japan. 0335218315 mfax : rmf ax0@email.sps.mot.com touchtone (602) 2446609 hong kong : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok road, tai po, n.t., hong kong. 85226629298 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. at ypicalo parameters can and do vary in dif ferent applications. all operating parameters, including at ypicalso must be validated for each customer application by customer ' s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur . should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af firmative action employer . mc54/74hct161a/d
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